1. Field of the Invention
The present invention relates to a liquid crystal display unit. In particular, it relates to an active matrix liquid crystal display unit.
2. Description of the Related Art
An active matrix liquid crystal display unit using a thin film transistor (abbreviated as TFT, hereinafter) as a switching element is widely used. Such an active matrix liquid crystal display unit comprises: a substrate on which gate wiring, drain wiring, TFTs, pixel electrodes and the like are disposed (referred to as a TFT substrate, hereinafter); an opposite substrate on which a color filter, a black matrix and the like are disposed; and a liquid crystal interposed between the substrates. Applying a voltage between the electrodes on the TFT substrate and the electrodes on the opposite substrate or between plural electrodes on the TFT substrate causes the orientations of the liquid crystal molecules, thereby controlling the light transmission on a pixel-to-pixel basis.
FIGS. 1, 2A and 2B show an exemplary structure of an active matrix liquid crystal display unit disclosed in Japanese Patent Laid-Open No. 8-330592. FIG. 1 is a plan view of a TFT substrate showing a configuration thereof near an intersection of gate wiring and drain wiring. FIGS. 2A and 2B are cross-sectional views thereof taken along the lines I-I and II-II in FIG. 1, respectively.
As shown in FIGS. 1, 2A and 2B, the TFT substrate comprises a transparent insulating substrate 1, gate wiring 2 on the transparent insulating substrate 1, and drain wiring 6 that perpendicularly intersects with the gate wiring 2 with a gate insulating film 3 interposed therebetween. At the intersection of the gate wiring 2 and the drain wiring 6, an island-like semiconductor layer is provided on the gate insulating film 3. The semiconductor layer comprises a lower amorphous silicon sublayer (referred to as an a-Si sublayer 4, hereinafter) and an upper n+a-Si sublayer 5 containing an n-type impurity in a relatively large amount. A TFT 11 is disposed near the intersection of the gate wiring 2 and the drain wiring 6. The TFT 11 comprises a gate electrode 2A, the gate insulating film 3, the a-Si sublayer 4, the n+a-Si sublayer 5, a drain electrode 6A and a source electrode 7. A channel section of the TFT 11 is formed by partially removing the n+a-Si sublayer 5 and the a-Si sublayer 4. The drain electrode 6A and the source electrode 7 are located on the opposite sides of the channel section. The drain electrode 6A and the gate electrode 2A of the TFT 11 are connected to the drain wiring 6 and the gate wiring 2, respectively. A pixel electrode 9, which is made of a transparent conductive film of indium tin oxide (ITO) or the like, is formed so as to partially overlap with the source electrode 7, and a passivation layer 8 for protecting the surface of the substrate is formed on the pixel electrode 9 and the source electrode 7.
In this way, in order to drive a matrix array of the TFTs 11, the TFT substrate has the gate wiring 2 and the drain wiring 6 disposed perpendicular to each other. If the TFT substrate has inverted-staggered TFTs 11, the drain wiring 6 is formed over the gate wiring 2. The drain wiring 6 is formed by depositing a metal material, such as Cr, by sputtering or the like. It is known that the Cr film deposited by sputtering is not dense and, in particular, is coarse in an area covering a step. Furthermore, sputtering cannot provide adequate step coverage, and thus, the resulting metal film, which is to constitute the drain wiring 6, is thinner on the side faces of the step on the gate insulating film 3 formed due to the gate wiring 2. Therefore, when the deposited metal film, which is to constitute the drain wiring 6, is wet-etched using a resist pattern as a mask, the etching process is completed faster in the side faces of the step, and the etchant penetrates into the interface between the gate insulating film 3 and the metal film at the step. As a result, a problem occurs that the drain wiring 6 is broken.
The Japanese Patent Laid-Open No. 8-330592 described above discloses a method of avoiding such defective etching of the upper wiring due to the step at the intersection of wires. According to the Japanese Patent Laid-Open No. 8-330592, as shown in FIG. 3, the gate wiring 2 (gate electrode 2A) and the semiconductor layers located below the drain wiring 6, the drain electrode 6A and the source electrode 7 have protrusions formed at the opposite sides thereof. It is described that the penetration path for the etchant is elongated by these protrusions, and thus, the drain wiring 6 can be prevented from being broken at the step formed due to the underlying gate wiring 2 and semiconductor layers.
In the liquid crystal display unit, the gate wiring and the drain wiring tend to be made thin to improve the aperture ratio. As the drain wiring becomes thinner, the penetration path for the etchant becomes shorter, and the wire becomes more likely to be broken. Besides, to reduce the parasitic capacitance between the gate wiring and the drain wiring, it is preferred that the gate wiring is as thin as possible at the intersection. However, in the Japanese Patent Laid-Open No. 8-330592 described above, no mention is made of the size of the protrusions. The protrusions formed on the gate wiring 2 described in the Japanese Patent Laid-Open No. 8-330592 cannot provide sufficient extension of the penetration path for the etchant. In addition, since the protrusions extending outwardly from the gate wiring 2 are formed along the drain wiring 6, the parasitic capacitance between the wires increases.
Furthermore, in the Japanese Patent Laid-Open No. 8-330592 described above, as can be seen from FIG. 3, the gate wiring 2 has substantially right-angled side faces, which are reflected in the drain wiring 6, and thus, the drain wiring 6 has a step having substantially right-angled side faces. The drain wiring 6 is composed of a metal film, specifically, a Cr film. At the side faces of the step, the metal film is covered inadequately, so that the metal film is thinner than in the remaining areas, and thus, the metal film is susceptible to penetration of the etchant. Thus, even if the protrusions are formed on the gate wiring 2 to elongate the penetration path for the etchant, it is difficult to prevent the drain wiring 6 from being broken with reliability.
As described above, if the drain wiring is thin to improve the definition of the liquid crystal display unit, it is necessary to optimize not only the two-dimensional configuration of the gate wiring at the intersection of the gate wiring and the drain wiring but also the three-dimensional configuration thereof in accordance with the width of the drain wiring.